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Complete Solution

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2022-10-07 02:51:44
Complete Solution

NOT Gate


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AND Gate

NOR Gate

OR Gate

Always On

Second Tick

XOR Gate

Bigger OR Gate


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Bigger AND Gate


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XNOR Gate

ODD Number Of Signals


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Double Trouble


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Counting Signals


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Double The Number


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Half Adder


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Full Adder


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Bit Switch


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Byte OR


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Byte NOT


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Adding Bytes


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Circular Dependency


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Delayed Lines


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Odd Ticks


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Saving Gracefully


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Bit Inverter


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Input Selector


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The Bus


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Saving Bytes


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1 Bit Decoder


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3 Bit Decoder

One Way


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Little Box


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Counter


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Negative Numbers


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Signed Negator


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Logic Engine


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Arithmetic Engine


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Registers

Instruction Decoder


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Calculations

Program

Immediate Values

Conditions


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Turing Complete

Add 5


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Calibrating Laser Canons

#Opcodes const add 0b01000100 const in_to_reg1 0b10110001 const reg1_to_reg2 0b10001010 const reg3_to_reg2 0b10011010 const reg3_to_out 0b10011110 #Add input 6 times with itself in_to_reg1 reg1_to_reg2 add reg3_to_reg2 add reg3_to_reg2 add reg3_to_reg2 add reg3_to_reg2 add reg3_to_out

Spacial Invasion

#Opcodes const reg0_to_out 0b10000110 const in_to_reg3 0b10110011 const if_zero 0b11000001 const always 0b11000100 const up 1 const wait 3 const shoot 5 shoot reg0_to_out up reg0_to_out reg0_to_out reg0_to_out reg0_to_out reg0_to_out label checkForRats in_to_reg3 doNothing if_zero shoot reg0_to_out checkForRats always label doNothing wait reg0_to_out checkForRats always

Storage Cracker

#Opcodes const reg0_to_reg1 0b10000001 const reg3_to_out 0b10011110 const reg3_to_reg2 0b10011010 const add 0b01000100 const always 0b11000100 1 reg0_to_reg1 label increase add reg3_to_out reg3_to_reg2 increase always

Masking Time

#Opcodes const in_to_reg1 0b10110001 const reg0_to_reg2 0b10000010 const reg3_to_out 0b10011110 const and 0b01000011 in_to_reg1 0b00000011 #Bit mask reg0_to_reg2 and reg3_to_out

The Maze

#Opcodes const reg0_to_out 0b10000110 const in_to_reg3 0b10110011 const always 0b11000100 const if_zero 0b11000001 const turn_left 0 const step 1 const turn_right 2 const openDoor 4 label walk step reg0_to_out turn_left reg0_to_out openDoor reg0_to_out in_to_reg3 walk if_zero label turnRight turn_right reg0_to_out openDoor reg0_to_out in_to_reg3 walk if_zero turnRight always

XOR

#Opcodes const in_to_reg1 0b10110001 const in_to_reg2 0b10110010 const reg3_to_reg4 0b10011100 const reg3_to_reg1 0b10011001 const reg4_to_reg2 0b10100010 const reg3_to_out 0b10011110 const or 0b01000000 const nand 0b01000001 const and 0b01000011 in_to_reg1 in_to_reg2 or reg3_to_reg4 nand reg3_to_reg1 reg4_to_reg2 and reg3_to_out

Byte XOR


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Byte Constant


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Equality


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Unsigned Less


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Signed Less


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Wide Instructions


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Wire Spaghetti


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Opcodes


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Immediate Values


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Conditionals


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RAM


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#Opcodes const set 0b11000000 const addi 0b01000000 const ifi_neq_jmp 0b01100001 const _ 0 const ADR 5 const CNT 6 const IO 7 const RAM 8 label fromInput addi IO _ RAM addi ADR 1 ADR ifi_neq_jmp ADR 32 fromInput set 0 _ ADR label toOutput addi RAM _ IO addi ADR 1 ADR ifi_neq_jmp ADR 32 toOutput

Shift


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The Product Of Nibbles


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Divide

#Opcodes const if_lt 0b00100010 const addi 0b01000000 const sub 0b00000001 const set 0b11000000 #Register const _ 0 const REG1 1 const REG2 2 const REG3 3 const CNT 6 const IO 7 addi IO _ REG1 addi IO _ REG2 label subtract if_lt REG1 REG2 output sub REG1 REG2 REG1 addi REG3 1 REG3 set subtract _ CNT label output addi REG3 _ IO addi REG1 _ IO

Delay


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Stack


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PUSH And POP


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Do the Lab first, to get the 2-Bit-Decoder, that i used in this solution.

#Opcodes const set 0b11000000 const addi 0b01000000 const ifi_eq_jmp 0b01100000 const _ 0 const REG1 1 const CNT 6 const IO 7 const STACK 16 label fromInput addi IO _ REG1 ifi_eq_jmp REG1 0 toOutput addi REG1 _ STACK set fromInput _ CNT label toOutput addi STACK _ IO set fromInput _ CNT

Functions


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AI Showdown

#Opcodes const set 0b11000000 const addi 0b01000000 const subi 0b01000001 const and 0b00000010 const _ 0 const REG0 0 const REG1 1 const CNT 6 const IO 7 set 0b00000011 _ REG1 #mod4 label takeCard addi IO _ REG0 subi REG0 1 REG0 and REG0 REG1 IO set takeCard _ CNT

Dancing Machine

Be sure your ALU is wired up properly after this change, because of the increase in area.

#Opcodes const shli 0b01000110 const shri 0b01000111 const xor 0b00000101 const and 0b00000010 const addi 0b01000000 const set 0b11000000 const _ 0 const SEED 0 const BRACKET 1 const TEMP1 2 const TEMP2 3 const MOD4 4 const CNT 6 const IO 7 addi IO _ SEED set 0b00000011 _ MOD4 label nextStep shri SEED 1 BRACKET xor SEED BRACKET TEMP1 shli TEMP1 1 BRACKET xor TEMP1 BRACKET TEMP2 shri TEMP2 2 BRACKET xor TEMP2 BRACKET SEED and SEED MOD4 IO set nextStep _ CNT

Planet Names

#Opcodes const set 0b11000000 const addi 0b01000000 const subi 0b01000001 const ifi_eq_jmp 0b01100000 const _ 0 const CHARACTER 0 const NEWWORD 1 const CNT 6 const IO 7 set 1 _ NEWWORD label nextChar addi IO _ CHARACTER ifi_eq_jmp NEWWORD 1 upperCase ifi_eq_jmp CHARACTER 32 reset addi CHARACTER _ IO set nextChar _ CNT label reset set 1 _ NEWWORD addi CHARACTER _ IO set nextChar _ CNT label upperCase subi CHARACTER 32 CHARACTER set 0 _ NEWWORD addi CHARACTER _ IO set nextChar _ CNT

Unseen Fruit

#Opcodes const addi 0b01000000 const set 0b11000000 const ifi_eq_jmp 0b01100000 const ifi_neq_jmp 0b01100001 const turnLeft 0 const step 1 const turnRight 2 const wait 3 const action 4 const CONVBELT 92 const _ 0 const SEEING 5 #RAM adr register const CNT 6 const IO 7 const RAM 8 # go to conveyor belt set turnRight _ IO set step _ IO set turnRight _ IO set step _ IO set step _ IO set step _ IO set step _ IO set turnRight _ IO set step _ IO set turnLeft _ IO set step _ IO label checkFood set wait _ IO addi IO _ SEEING ifi_eq_jmp SEEING CONVBELT checkFood ifi_neq_jmp RAM 0 alarm set 1 _ RAM #set seen set checkFood _ CNT label alarm set turnRight _ IO set action _ IO

Delicious Order

#Opcodes const set 0b11000000 const addi 0b01000000 const subi 0b01000001 const ifi_neq_jmp 0b01100001 const ifi_gt_jmp 0b01100100 const ifi_eq_jmp 0b01100000 const _ 0 const NUMREADS 1 const ADR 5 const CNT 6 const IO 7 const RAM 8 set 15 _ NUMREADS label readValues addi IO _ ADR addi RAM 1 RAM subi NUMREADS 1 NUMREADS ifi_neq_jmp NUMREADS 0 readValues set 0 _ ADR label output ifi_gt_jmp RAM 0 outputRam ifi_eq_jmp RAM 0 incAdr set output _ CNT label outputRam addi ADR _ IO subi RAM 1 RAM set output _ CNT label incAdr addi ADR 1 ADR set output _ CNT

Robot Racing

#Opcodes const set 0b11000000 const _ 0 const r 0 const d 1 const l 2 const u 3 const io 7 set u _ io set r _ io set d _ io set r _ io set r _ io set u _ io set l _ io set u _ io set r _ io set u _ io set l _ io set l _ io set d _ io set l _ io set u _ io set u _ io set r _ io set u _ io set l _ io set u _ io set u _ io set r _ io set d _ io set r _ io set u _ io set r _ io set d _ io set d _ io set l _ io set d _ io set r _ io set r _ io set r _ io set u _ io set l _ io set u _ io set u _ io set r _ io set d _ io set r _ io set u _ io set r _ io set d _ io set d _ io set l _ io set d _ io set r _ io set d _ io set d _ io set l _ io set u _ io set l _ io set l _ io set d _ io set r _ io set d _ io set l _ io set d _ io set r _ io set r _ io set u _ io set r _ io set d _ io set d _ io

Tower Of Alloy

#Opcodes const addi 0b01000000 const subi 0b01000001 const ifi_neq_jmp 0b01100001 const set 0b11000000 const call 0b11101110 const ret 0b11110110 const _ 0 const disc_nr 0 const source 1 const dest 2 const spare 3 const io 7 const stack 16 const magToggle 5 addi io _ stack addi io _ stack addi io _ stack addi io _ stack label move call _ _ loadMyVars ifi_neq_jmp disc_nr 0 else call _ _ magnet ret _ _ _ label else call _ _ storeMyVars subi disc_nr 1 stack addi source _ stack addi spare _ stack addi dest _ stack call _ _ move call _ _ loadMyVars call _ _ magnet call _ _ storeMyVars subi disc_nr 1 stack addi spare _ stack addi dest _ stack addi source _ stack call _ _ move call _ _ loadMyVars ret _ _ _ label magnet addi source _ io set magToggle _ io addi dest _ io set magToggle _ io ret _ _ _ label loadMyVars addi stack _ spare addi stack _ dest addi stack _ source addi stack _ disc_nr ret _ _ _ label storeMyVars addi disc_nr _ stack addi source _ stack addi dest _ stack addi spare _ stack ret _ _ _

Water World

#Opcodes const set 0b11000000 const addi 0b01000000 const subi 0b01000001 const add 0b00000000 const sub 0b00000001 const if_gt_call 0b00101100 const ifi_neq_jmp 0b01100001 const if_lt_call 0b00101010 const ret 0b11110110 const _ 0 const num_reads 0 const currVal 1 const max_left 2 const max_right 3 const sum 4 const adr 5 const io 7 const ram 8 set 16 _ num_reads label readValues addi io _ ram addi adr 1 adr subi num_reads 1 num_reads ifi_neq_jmp num_reads 0 readValues set 0 _ adr set 16 _ num_reads label readFromLeft addi ram _ currVal if_gt_call currVal max_left setMaxLeft addi adr 16 adr sub max_left currVal ram subi adr 15 adr subi num_reads 1 num_reads ifi_neq_jmp num_reads 0 readFromLeft set 15 _ adr set 16 _ num_reads label readFromRight addi ram _ currVal if_gt_call currVal max_right setMaxRight sub max_right currVal currVal addi adr 16 adr if_lt_call currVal ram setActual subi adr 17 adr subi num_reads 1 num_reads ifi_neq_jmp num_reads 0 readFromRight set 16 _ adr set 16 _ num_reads label sumValues add sum ram sum addi adr 1 adr subi num_reads 1 num_reads ifi_neq_jmp num_reads 0 sumValues addi sum _ io label setMaxLeft addi currVal _ max_left ret _ _ _ label setMaxRight addi currVal _ max_right ret _ _ _ label setActual addi currVal _ ram ret _ _ _

Source: https://steamcommunity.com/sharedfiles/filedetails/?id=2823205958

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